Semiconductor memory devices for storing data can typically be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, however nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Thus, nonvolatile memory devices are widely used in applications where the possibility of power supply interruption is present.
These nonvolatile memory devices are classified into two groups. One is a NAND-type flash memory device and the other is a NOR-type flash memory device. Either of them adapts a cell transistor having a stacked gate. The stacked gate comprises a floating gate and a control gate electrode, which are sequentially stacked on a semiconductor substrate.
A tunnel oxide layer is interposed between the semiconductor substrate and the floating gate, and an inter-gate dielectric layer is interposed between the floating gate and the control gate electrode. Accordingly, the inter-gate dielectric layer as well as the tunnel oxide layer should be reliable in order to improve a data retention characteristic and the like.
FIG. 1 is a plan view for illustrating a typical flash memory device having a cell transistor and a peripheral transistor in a cell array region and in a peripheral circuit region, respectively.
Referring to FIG. 1, a plurality of first active regions 20 defined by an isolation layer (not shown) are disposed in a cell array region a of a semiconductor substrate. A plurality of parallel control gate electrodes 109 (or 309) cross over the first active regions 20. A floating gate F1 (F3′ or F4′) is interposed between the first active region 20 and the control gate electrode 109 (or 309). The floating gate F1 (F3′ or F4′) is extended to overlap with the edge of the isolation layer. A tunnel oxide layer (not shown) is interposed between the floating gate F1 (F3′ or F4′) and the first active region 20, and an inter-gate dielectric layer (not shown) is interposed between the floating gate F1 (F3′ or F4′) and the control gate electrode 109 (or 309). The inter-gate dielectric layer may be extended along the control gate electrode 109 (or 309).
Similarly, a second active region 30 defined by the isolation layer is disposed in a peripheral circuit region b of the semiconductor substrate. A gate electrode 110 (310 or 410) crosses over the second active region 30.
FIGS. 2A through 6A are cross sectional views for illustrating a conventional method of fabricating a flash memory device, taken along the line I-I ′ of FIG. 1. Also, FIGS. 2B through 6B are cross sectional views for illustrating a conventional method of fabricating a flash memory device, taken along the line II-II′ of FIG. 1.
Referring to FIGS. 2A and 2B, a device isolation layer 101 is formed at a predetermined region of a semiconductor substrate 100 to define first active regions (20 of FIG. 1) and a second active region (30 of FIG. 1) in a cell array region a and a peripheral circuit region b, respectively.
Referring to FIGS. 3A and 3B, a tunnel oxide layer 102 and a first conductive layer 103 are formed on the entire surface of the semiconductor substrate having the isolation layer 101. The first conductive layer 103 is patterned to form a floating gate pattern F1 covering the first active regions (20 of FIG. 1). At this time, the peripheral circuit region b is still covered with the first conductive layer 103.
An inter-gate dielectric layer 106 is then formed on the entire surface of the substrate including the floating gate pattern F1.
Referring to FIGS. 4A and 4B, the inter-gate layer 106, the first conductive layer 103 and the tunnel oxide layer 102 on the peripheral circuit region b are selectively removed, thereby exposing the isolation layer 101 and the second active region (30 of FIG. 1) in the peripheral circuit region b.
Referring to FIGS. 5A and 5B, a surface impurity diffusion layer (not shown) for adjusting a threshold voltage of a peripheral transistor is formed at the second active region of the peripheral circuit region b, and a gate oxide layer 105 is formed on the exposed second active region.
Afterwards a gate conductive layer 107 and a metal silicide layer 108 are sequentially formed on the entire surface of the substrate, whose portion b has the gate oxide layer 105.
Referring to FIGS. 6A and 6B, the metal silicide layer 108, the gate conductive layer 107, the inter-gate dielectric layer 106 and the floating gate pattern F1, which are located in the cell array region a, are sequentially patterned. As a result, a control gate electrode 109 crossing over the first active regions (20 of FIG. 1) is formed, and a floating gate F1′ interposed between the control gate electrode 109 and the first active region (20 of FIG. 1) is formed.
Moreover, the metal silicide layer 108 and the gate conductive layer 107, which are located in the peripheral circuit region b, are successively patterned to form a gate electrode 110 crossing over the second active region (30 of FIG. 1). Impurity ions are implanted into the semiconductor substrate 100, thereby forming source/drain regions 113 and 114 in the cell array region a and the peripheral circuit region b. Interlayer insulating layer 111 is then formed on the entire surface of the substrate having the source/drain regions 113 and 114. The interlayer insulating layer 111 is patterned to form a contact hole 112 exposing the gate electrode 110.
Thus, the crucial inter-gate dielectric layer 106 of the conventional flash memory device is exposed from transitioning between FIGS. 4A, 4B to FIGS. 5A, 5B. In other words, the inter-gate dielectric layer 106 is exposed during a process of selective exposing of the second active region and the isolation layer in the peripheral circuit region b, a process of ion implantation, and a process of forming the gate oxide layer. The ion implantation process is necessary to adjust the threshold voltage of the peripheral transistor.
Since it is exposed, the crucial inter-gate dielectric layer 106 can be easily contaminated with heavy metal atoms in a photoresist layer, which is used in the patterning process. This contamination leads to a degradation of the inter-gate dielectric layer 106. In other words, the contamination makes the inter-gate dielectric layer 106 leaky. Accordingly, the reliability such as the data retention characteristic or the endurance characteristic to the erase/program cycles is deteriorated.
FIGS. 7A and 7B are schematic cross sectional views illustrating another conventional flash memory. The cell array region a has the same structure as that of the conventional flash memory device described in FIGS. 2A-6A and 2B-6B.
A difference, however, is that the peripheral circuit region b has a stacked gate pattern 210. The stacked gate pattern 210 comprises a gate electrode 103, an inter-gate dielectric layer 106, a gate conductive layer 107 and a metal silicide layer 108, which are sequentially stacked on the gate oxide layer 105. The gate conductive layer 107 and the metal silicide layer 108 constitute a dummy gate electrode. The dummy gate electrode and the gate electrode 103 are exposed by a butting contact 212 penetrating a portion of the interlayer insulating layer 111.
The butting contact technique requires a complex process. Thus, there continues to be a need for simple and reliable method of fabricating flash memory devices.